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ANR Research Project - Lord of the RISCs

Lord Of The RISCs (LOTR) is a novel flow for designing highly customized RISC-V processor microarchitectures for embedded and IoT platforms. The LOTR flow operates on a description of the processor Instruction Set Architecture (ISA). It can automatically infer synthesizable Register Transfer Level (RTL) descriptions of a large number of microarchitecture variants with different performance/cost trade-offs. In addition, the flow integrates two domain-specific toolboxes dedicated to the support of timing predictability (for safety-critical systems) and security (through hardware protection mechanisms).

Main features of LOTR

Specify, test and debug your processor’s ISA using high-level programmation language

Explore a large design space of processor implementations from a single ISS, thanks to speculative pipelining and high-level synthesis

Define and ensure non-functionnal properties on the generated hardware (e.g. security and timing properties)

Overview of the transformation flow

LOTR flow is based on four different abstractions levels, all detailed on the figure below:


The Instruction Set Level is used to represent the functionnal behaviour of your processor, and is directly derived from the user-provided specifications. The Abstract Pipeline Level adds new variables which represents micro-architectural state of the processor (e.g. branch prediction, cache or interlocking mechanisms for simple pipelined processor). The *Cycle Accurate Level" is a representation where we applied Speculative Loop Pipelining to the previous representation and obtained a new design where an iteration represents a cycle in the final processor. The Structural Pipeline Level is obtained by scheduling all operations and performing register retiming.


Damien Courroussé

Steven Derrien

Jean-Michel Gorius

Mathieu Jan

Dylan Leothaud

Isabelle Puaut

Simon Rokicki